With advances in computing technology, computing devices are smaller and have much more processing power. Additionally, they include more and more storage and memory to meet the needs of the programming and computing performed on the devices. The shrinking size of the devices together with the increased storage capacity is achieved by providing higher density devices, where the atomic storage units (memory cells) within a memory device have smaller and smaller geometries.
With the latest generations of increased density, intermittent failure has appeared in some devices. For example, some existing DDR3 (dual data rate version 3) DRAM (dynamic random access memory) based systems experience intermittent failures with heavy workloads. Researchers have traced the failures to repeated access to a single row of memory within the refresh window of the memory cell. For example, for a 32 nm process in a DDR3 DRAM, if a row is accessed 550K times or more in the 64 millisecond refresh window, the physically adjacent wordline to the accessed row has a very high probability of experiencing data corruption. The row hammering or repeated access to a single row can cause migration across the passgate. The leakage and parasitic currents caused by the repeated access to one row cause data corruption in a non-accessed physically adjacent row. The failure issue has been labeled as a ‘row hammer’ or ‘1 row disturb’ issue by the DRAM industry where it is most frequently seen.
One of the intermittent failures that can occur due to a row hammer condition is related to the fact memory devices are typically organized in ranks on a DIMM (dual inline memory module). The memory devices on the DIMM share a command/address (C/A) bus. When an associated memory controller issues a command for a memory access operation, all memory devices in the rank access a row of memory in response to the command. Thus, when a failure occurs due to a row hammer condition, the failure can occur in the same row of all the memory devices. While memory devices typically have data recovery mechanisms in place, failure concurrently in all the memory devices can prevent recovery of data due to the fact that all memory devices fail at the same row.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.